 |
GS81284Z18/36
|
|
|
|
|
FT
Access
Time
(ns)
|
|
|
|
|
|
|
Verilog
|
BSDL
|
VHDL
|
IBIS |
|
|
4M
x 36
|
PL/FT
|
2.5/3.3
V
|
5.5, 6.5, 7.5, 8 |
250, 200, 167 |
B/GB |
Pre-Qual |
|
n/a |
n/a |
n/a |
n/a |
|
|
8M
x 18
|
PL/FT
|
2.5/3.3
V
|
5.5, 6.5, 7.5, 8 |
250, 200, 167 |
B/GB |
Pre-Qual |
|
n/a |
n/a |
n/a |
n/a |
*Notes:
Spice models may be requested from our Applications Engineering Department here.
Denali models can be found here.
Synopsys models can be found here.
| Features |
.
FT pin for user-configurable flow through or pipeline operation
. NBT functionality allows zero wait read-write-read
bus utilization
. Fully pin-compatible NtRAM™, NoBL™, and ZBT™ SRAMs
. 2.5 V or 3.3 V +10%/-10% core power supply
. 2.5 V or 3.3 V I/O supply
. LBO pin for Linear or Interleaved Burst mode |
. Internal input resistors on mode pins allow floating mode pins
. Byte Write (BW) and/or Global Write (GW) operation
. Internal self-timed write cycle
. Automatic power-down for portable applications
. JEDEC-standard BGA package |
|
