 |
GS8161(E)18/32/36B
|
|
|
|
|
FT
Access
Time
(ns)
|
|
|
|
|
|
|
Verilog
|
BSDL
|
VHDL
|
IBIS |
|
|
512K
x 36
|
PL/FT
|
2.5/3.3
V
|
5.5, 6.5,
7.5
|
250,
200, 150
|
T/D/
GT/GD
|
Prod
|
|
n/a
|
n/a
|
(D) |
(D) |
(T) |
(T) |
|
|
512K
x 32
|
PL/FT
|
2.5/3.3
V
|
5.5, 6.5,
7.5
|
250,
200, 150
|
D/
GD
|
Prod
|
|
n/a
|
n/a
|
n/a
|
|
|
|
1M
x 18
|
PL/FT
|
2.5/3.3
V
|
5.5, 6.5,
7.5
|
250,
200, 150
|
T/D/
GT/GD
|
Prod
|
|
n/a
|
n/a
|
(D) |
(D) |
(T) |
(T) |
|
512K x 36 |
PL/FT |
2.5/3.3 V |
5.5, 6.5,
7.5 |
250,
200, 150 |
T/D/
GT/GD |
Prod |
|
n/a |
n/a |
(D) |
n/a |
(T) |
|
512K x 32 |
PL/FT |
2.5/3.3 V |
5.5, 6.5,
7.5 |
250,
200, 150 |
D/
GD |
Prod |
|
n/a |
n/a |
n/a |
n/a |
|
1M x 18 |
PL/FT |
2.5/3.3 V |
5.5, 6.5,
7.5 |
250,
200, 150 |
T/D/
GT/GD |
Prod |
|
n/a |
n/a |
(D) |
n/a |
(T) |
*Notes:
Spice models may be requested from our Applications Engineering Department here.
Denali models can be found here.
Synopsys models can be found here.
| Features |
.
FT pin for user-configurable flow through or pipeline operation
. Single Cycle Deselect operation (GS816118/32/36B)
. Dual Cycle Deselect operation (GS8161E18/32/36B)
. ZQ mode pin for user-selectable high/low output drive
. 2.5 V or 3.3 V +10%/-10% core power supply
. 2.5 V or 3.3 V I/O supply |
.
LBO pin for Linear or Interleaved Burst mode
. Internal input resistors on mode pins allow floating mode pins
. Byte Write (BW) and/or Global Write (GW) operation
. Internal self-timed write cycle
. Automatic power-down for portable applications
. JEDEC-standard package; available in RoHS-compliant package
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