 |
GS816272
|
|
|
|
|
FT
Access
Time
(ns)
|
|
|
|
|
|
|
Verilog
|
BSDL
|
VHDL
|
IBIS |
|
|
256K
x 72
|
PL/FT
|
2.5/3.3
V
|
6.5, 7,
7.5, 8.5
|
200, 166, 150, 133
|
C
|
|
|
|
|
|
n/a |
*Notes:
Spice models may be requested from our Applications Engineering Department here.
Denali models can be found here.
Synopsys models can be found here.
| Features |
.
FT pin for user-configurable flow through or pipeline operation
. Single Cycle Deselect operation (GS816018/32/36B)
. Dual Cycle Deselect operation (GS8160E18/32/36B)
. ZQ mode pin for user-selectable high/low output drive
. 2.5 V or 3.3 V +10%/-10% core power supply
. 2.5 V or 3.3 V I/O supply |
.
LBO pin for Linear or Interleaved Burst mode
. Internal input resistors on mode pins allow floating mode pins
. Byte Write (BW) and/or Global Write (GW) operation
. Internal self-timed write cycle
. Automatic power-down for portable applications
. JEDEC-standard package |
|
