 |
GS8180QV18/36B
|
|
|
|
FT Access
Time
(ns) |
|
|
|
|
|
Verilog |
BSDL |
VHDL |
IBIS |
|
512K x 36 |
PL |
2.5 V VDD;
1.5/1.8 V I/O |
n/a |
200, 167 |
D/
GD |
In Dev |
|
n/a |
n/a |
n/a |
n/a |
|
1M x 18 |
PL |
2.5 V VDD;
1.5/1.8 V I/O |
n/a |
200, 167 |
D/
GD |
In Dev |
|
n/a |
n/a |
n/a |
n/a |
*Notes:
Spice models may be requested from our Applications Engineering Department here.
Denali models can be found here.
Synopsys models can be found here.
| Features |
. Simultaneous Read and Write SigmaQuad Interface
. JEDEC-standard pinout and package
. Dual Double Data Rate Interface
. Burst of 2 Read and Write
. 2.5 V core power supply
. 1.5 V or 1.8 V I/O supply |
. Pipelined Read operation
. Fully coherent Read and Write pipelines
. ZQ mode pin for programmable output drive strength
. IEEE 1149.1 JTAG-compliant Boundary Scan
. 165-Bump, 13 mm x 15 mm, 1 mm bump pitch BGA package
. RoHS-compliant package available |
|
