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GS8321(E)18/32/36A-xxxV
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FT Access
Time
(ns) |
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Verilog |
BSDL |
VHDL |
IBIS |
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1M x 36 |
PL/FT |
1.8/2.5 V |
5.0, 5.5, 6.5, 7.5 |
333, 250, 200, 150 |
D/
GD |
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1M x 32 |
PL/FT |
1.8/2.5 V |
5.0, 5.5, 6.5, 7.5 |
333, 250, 200, 150 |
D/
GD |
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2M x 18 |
PL/FT |
1.8/2.5 V |
5.0, 5.5, 6.5, 7.5 |
333, 250, 200, 150 |
D/
GD |
|
|
|
|
|
 |
|
1M x 36 |
PL/FT |
1.8/2.5 V |
5.0, 5.5, 6.5, 7.5 |
333, 250, 200, 150 |
D/
GD |
|
|
|
|
|
|
|
1M x 32 |
PL/FT |
1.8/2.5 V |
5.0, 5.5, 6.5, 7.5 |
333, 250, 200, 150 |
D/
GD |
|
|
|
|
|
|
|
2M x 18 |
PL/FT |
1.8/2.5 V |
5.0, 5.5, 6.5, 7.5 |
333, 250, 200, 150 |
D/
GD |
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*Notes:
Spice models may be requested from our Applications Engineering Department here.
Denali models can be found here.
Synopsys models can be found here.
| Features |
.
FT pin for user-configurable flow through or pipeline operation
. Single Cycle Deselect operation (GS832118/32/36A)
. Dual Cycle Deselect operation (GS8321E18/32/36A)
. ZQ mode pin for user-selectable high/low output drive
. 1.8 V or 2.5 V +10%/-10% core power supply
. 1.8 V or 2.5 V I/O supply |
.
LBO pin for Linear or Interleaved Burst mode
. Internal input resistors on mode pins allow floating mode pins
. Byte Write (BW) and/or Global Write (GW) operation
. Internal self-timed write cycle
. Automatic power-down for portable applications
. JEDEC-standard package; available in RoHS-compliant package
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