 |
GS841(E)18A
|
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|
|
FT Access
Time
(ns) |
|
|
|
|
|
Verilog |
BSDL |
VHDL |
IBIS |
|
256K x 18 |
PL/FT |
3.3 V VDD; 2.5/3.3 V I/O |
8.5, 10, 11, 12 |
166, 150, 133, 100 |
T/B/GT/GB |
Prod |
|
|
(B) |
n/a |
n/a |
(T) |
|
256K x 18 |
PL/FT |
3.3 V VDD; 2.5/3.3 V I/O |
8.5, 10, 11, 12 |
166, 150, 133, 100 |
T/B/GT/GB |
Prod |
|
n/a |
n/a |
n/a |
n/a |
*Notes:
Spice models may be requested from our Applications Engineering Department here.
Denali models can be found here.
Synopsys models can be found here.
| Features |
.
FT pin for user-configurable flow through or pipeline operation
. Tag RAM
. Dual Cycle Deselect operation (GS841E18A)
. ZQ mode pin for user-selectable high/low output drive
. 2.5 V or 3.3 V +10%/-10% core power supply
. 2.5 V or 3.3 V I/O supply |
.
LBO pin for Linear or Interleaved Burst mode
. Internal input resistors on mode pins allow floating mode pins
. Byte Write (BW) and/or Global Write (GW) operation
. Internal self-timed write cycle
. Automatic power-down for portable applications
. JEDEC-standard package; available in RoHS-compliant package
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