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GS8662T08/09/18/36
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FT Access
Time
(ns) |
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Verilog |
BSDL |
VHDL |
IBIS |
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2M x 36 |
PL |
1.8 V VDD;
1.5/1.8 V I/O |
n/a
|
333, 300, 250, 200, 167 |
E/GE |
Prod |
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|
n/a |
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4M x 18 |
PL |
1.8 V VDD;
1.5/1.8 V I/O |
n/a |
333, 300, 250, 200, 167 |
E/GE |
Prod |
|
|
|
n/a |
|
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8M x 9 |
PL |
1.8 V VDD;
1.5/1.8 V I/O |
n/a |
333, 300, 250, 200, 167 |
E/GE |
Prod |
|
|
|
n/a |
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8M x 8 |
PL |
1.8 V VDD;
1.5/1.8 V I/O |
n/a |
333, 300, 250, 200, 167 |
E/GE |
Prod |
|
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|
n/a |
 |
*Additional Resources:
TimingDesigner component libraries can be found here.
SPICE models may be requested from our Applications Engineering Department here.
Denali models can be found here.
Synopsys models can be found here.
| Features |
.
Simultaneous Read and Write SigmaQuad Interface
. JEDEC-standard pinout and package
. Dual Double Data Rate Interface
. Burst of 2 Read and Write
. 1.8 V core power supply
. 1.5 V or 1.8 V I/O supply |
.
Pipelined Read operation
. Fully coherent Read and Write pipelines
. ZQ mode pin for programmable output drive strength
. IEEE 1149.1 JTAG-compliant Boundary Scan
. 165-Bump, 15 mm x 17 mm, 1 mm bump pitch BGA package
. RoHS-compliant package available
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