 |
GS8673EQ18/36B
|
|
|
|
Read Latency
(RL) |
Operating
Frequency
(MHz)
|
|
|
|
|
Verilog |
BSDL |
VHDL |
IBIS |
GS8673EQ18/36BK-675
|
2M x 36
4M x 18 |
PL |
1.35 V VDD;
1.2/1.5 V I/O |
3.0, 2.0
|
675, 450 |
K/GK |
Production |
|
|
|
|
|
GS8673EQ18/36BK-625
|
2M x 36
4M x 18 |
PL |
1.35 V VDD;
1.2/1.5 V I/O |
3.0, 2.0
|
625, 400 |
K/GK |
Production |
|
|
|
|
|
GS8673EQ18/36BK-550
|
2M x 36
4M x 18 |
PL |
1.35 V VDD;
1.2/1.5 V I/O |
3.0, 2.0
|
550, 375 |
K/GK |
Production |
|
|
|
|
|
GS8673EQ18/36BK-500
|
2M x 36
4M x 18 |
PL |
1.35 V VDD;
1.2/1.5 V I/O |
3.0, 2.0 |
500, 333 |
K/GK |
Production |
|
|
|
|
|
*Additional Resources:
SPICE models may be requested from our Applications Engineering Department here.
| Features |
.
Simultaneous Read and Write SigmaQuad Interface
. JEDEC-standard package
. Dual Double Data Rate Interface
. Burst of 2 Read and Write
. 1.25 V or 1.35 V core power supply
. 1.2 V to 1.5 V I/O supply |
.
Pipelined Read operation
. Fully coherent Read and Write pipelines
. ZQ mode pin for programmable output drive strength
. IEEE 1149.1 JTAG-compliant Boundary Scan
. 260-Bump, 1 mm bump pitch BGA package |
|
