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GS881(E)18/32/36B-xxxV
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FT
Access
Time
(ns)
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Verilog
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BSDL
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VHDL
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IBIS |
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512K
x 36
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PL/FT
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1.8/2.5
V
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5.5, 6.5,
7.5
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250,
200, 150
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T/D/
GT/GD
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Prod
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n/a |
n/a |
n/a |
n/a |
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512K
x 32
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PL/FT
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1.8/2.5
V
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5.5, 6.5,
7.5
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250,
200, 150
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T/D/
GT/GD
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Prod
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n/a |
n/a |
n/a |
n/a |
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1M
x 18
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PL/FT
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1.8/2.5
V
|
5.5, 6.5,
7.5
|
250,
200, 150
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T/D/
GT/GD
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Prod
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n/a |
n/a |
n/a |
n/a |
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512K x 36 |
PL/FT |
1.8/2.5 V |
5.5, 6.5,
7.5 |
250,
200, 150 |
T/D/
GT/GD |
Prod |
|
n/a |
n/a |
n/a |
n/a |
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512K x 32 |
PL/FT |
1.8/2.5 V |
5.5, 6.5,
7.5 |
250,
200, 150 |
T/D/
GT/GD |
Prod |
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n/a |
n/a |
n/a |
n/a |
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1M x 18 |
PL/FT |
1.8/2.5 V |
5.5, 6.5,
7.5 |
250,
200, 150 |
T/D/
GT/GD |
Prod |
|
n/a |
n/a |
n/a |
n/a |
*Notes:
Spice models may be requested from our Applications Engineering Department here.
Denali models can be found here.
Synopsys models can be found here.
| Features |
.
FT pin for user-configurable flow through or pipeline operation
. Single Cycle Deselect operation (GS88118/32/36B)
. Dual Cycle Deselect operation (GS881E18/32/36B)
. ZQ mode pin for user-selectable high/low output drive
. 1.8 V or 2.5 V +10%/-10% core power supply
. 1.8 V or 2.5 V I/O supply |
.
LBO pin for Linear or Interleaved Burst mode
. Internal input resistors on mode pins allow floating mode pins
. Byte Write (BW) and/or Global Write (GW) operation
. Internal self-timed write cycle
. Automatic power-down for portable applications
. JEDEC-standard package; available in RoHS-compliant package
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