 |
GS882Z18/36C
|
|
|
|
FT Access
Time
(ns) |
|
|
|
|
|
Verilog |
BSDL |
VHDL |
IBIS |
|
256K x 36 |
PL/FT |
2.5/3.3 V |
4.5, 5, 5.5,
6.5, 7.5 |
333, 300, 250,
200, 150 |
B/D/
GB/GD |
Prod |
|
(B) |
(B) |
(B) |
|
(D) |
(D) |
(D) |
|
512K x 18 |
PL/FT |
2.5/3.3 V |
4.5, 5, 5.5,
6.5, 7.5 |
333, 300, 250,
200, 150 |
B/D/
GB/GD |
Prod |
|
(B) |
(B) |
(B) |
|
(D) |
(D) |
(D) |
*Notes:
Spice models may be requested from our Applications Engineering Department here.
Denali models can be found here.
Synopsys models can be found here.
| Features |
.
FT pin for user-configurable flow through or pipeline operation
. NBT functionality allows zero wait read-write-read
bus utilization
. Fully pin-compatible NtRAM™, NoBL™, and ZBT™ SRAMs
. 2.5 V or 3.3 V +10%/-10% core power supply
. 2.5 V or 3.3 V I/O supply
. LBO pin for Linear or Interleaved Burst mode |
. Internal input resistors on mode pins allow floating mode pins
. Byte Write (BW) and/or Global Write (GW) operation
. Internal self-timed write cycle
. Automatic power-down for portable applications
. JEDEC-standard package; available in RoHS-compliant package
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