The Bandwidth Engine® architecture is a highly parallel, multi-bank, multi-ported 1T-SRAM based memory array coupled with a high efficiency serial interface and on-board functionality, delivering intelligent scheduled access in addition to the highest memory transaction rate, table read rate and data throughput of any single chip device. Contact us for more information.
BANDWIDTH ENGINE 2
• 576Mb 1T-SRAM® memory array architecture
• 2.6 ns core cycle time, <16 ns read latency
• Low latency SerDes technology up to 15.625Gbps
• Up to 16 serial transceivers (TX/RX)
• High performance GigaChip® Interface
• High efficiency format utilizing scrambling
• CRC error detection and automatic recovery
• Intelligent Error Management and Bit Safe® Technology
The burst functionality of GSI Technology’s GSR622 provides up to 400Gbps CRC-protected, data throughput. Burst length is selectable on a cycle-by-cycle basis for maximum flexibility.
RECORD PROCESSING OFFLOAD ENGINE
GSI Technology’s Bandwidth Engine GSR820 adds on-board intelligence to the burst and access abilities of the GSR622, providing intelligent ofﬂoad for Counting, Statistics, Metering and Atomic operations. The highly parallel array architecture is capable of up to six billion memory accesses per second and can be saturated with only 8 SerDes lanes when utilizing the on-board macro functionality. Coupled with the efﬁcient, packetized, serial interface, it enables support of multiple applications within the 576Mbit footprint.