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Featured Patents Associative Computing Patents Memory Patents

Featured Recent Patents

 

Patent Number
10,958,272
Grant Date
3/23/2021
Title
Computation Memory Cells and Processing Array Device Using Complementary Exclusive or Memory Cells
Abstract

A memory cell and processing array that has a plurality of memory are capable of performing logic functions, including an exclusive OR (XOR) or an exclusive NOR (XNOR) logic function. The memory cell may have a read port in which the digital data stored in the storage cell of the memory cell isolated from the read bit line...Read More

Patent Number
10,956,432
Grant Date
3/23/2021
Title
 One-by-One Selection of Items of a Set
Abstract

A method and a system for selecting items one-by-one from a set of items in an associative memory array including determining a density of the set, if the density is sparse, repeatedly performing an extreme item select (EIS) method to select a next one of the elected items from the set and removing the next one from the set...Read More

Patent Number
10,949,766
Grant Date
3/16/20210
Title
Precise Exponent and Exact Softmax Computation
Abstract

A method for an associative memory device includes dividing a multi-bit mantissa A of a number X to a plurality of smaller partial mantissas Aj, offline calculating a plurality of partial exponents F(Aj) for each possible value of each partial mantissa Aj and storing the plurality of partial exponents F(Aj) in a look up table (LUT)...Read More

Patent Number
10,943,648
Grant Date
3/9/2021
Title
Ultra low VDD Memory Cells with Ratioless Write Port
Abstract

An ultra low VDD memory cell has a ratioless write port. In some embodiments, the VDD operation level can be as low as the threshold voltage of NMOS and PMOS transistors of the cell...Read More

 

Patent Number
10,942,736
Grant Date
3/9/2021
Title
Method for Min-Max Computation in Associative Memory
Abstract

A method for finding an extreme value among a plurality of numbers in an associative memory includes creating a spread-out representation (SOR) for each number of the plurality of numbers, storing each SOR in a column of the associative memory and performing a horizontal bit-wide...Read More

Patent Number
10,930,341
Grant Date
2/23/2021
Title
 Processing Array Device that Performs One Cycle Full Adder Operation and Bit Line Read/Write Logic Features
Abstract

A processing array that performs one cycle full adder operations.  The processing array may have different bit line read/write logic that permits different operations to be performed...Read More

 

Patent Number
10,929,751
Grant Date
2/23/2021
Title
Finding K Extreme Values in Constant Processing Time
Abstract

A method that includes determining a set of k extreme values of a dataset of elements in a constant time irrespective of the size of the dataset. A method that creates a set of k indicators, each indicator associated with one multi-bit binary number in a large dataset of multi-bit binary numbers...Read More

Patent Number
10,922,169
Grant Date
2/16/2021
Title
Error Detecting Memory Device
Abstract

A memory device includes a non-destructive memory array that includes memory cells arranged in rows and columns.  The array includes a plurality of word lines, first bit lines and second bit lines, and a NOR gate per column. Each word line activates memory cells in a row and thereby establishes...Read More

Patent Number
10,891,991
Grant Date
1/12/2021
Title
Massively Parallel, Associative Multiplier Accumulator
Abstract

An in-memory multiplier-accumulator includes a memory array, a multi-bit multiplier and a multi-bit layered adder.  The memory array has a multiplicity of rows and columns, each column being divided into a plurality of bit line processors and each bit line processor operating on its...Read More

Patent Number
10,891,076
Grant Date
1/12/2021
Title
Results Processing Circuits and Methods Associated with Computational Memory Cells
Abstract

A read and write data processing apparatus and method associated with computational memory cells formed as a memory/processing array (having a plurality of bit line sections) provides a mechanism to logically combine the computation results across multiple bit line sections in a...Read More

 

Associative Computing Patents

 

Type of Patent Patent Number Title Grant Date Abstract
APU 10,877,731 Processing array device that performs one cycle full adder operation and bit line read/write logic features 12/29/2020 More Info
APU 10,860,320 Orthogonal data transposition system and method during data transfers to/from a processing array 12/8/2020 More Info
APU 10,860,318 Computational memory cell and processing array device using memory cells 12/8/2020 More Info
APU 10,854,284 Computational memory cell and processing array device with ratioless write port 12/1/2020 More Info
APU

10,847,213

Write data processing circuits and methods associated with computational memory cells

11/24/2020

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APU

10,847,212

Read and write data processing circuits and methods associated with computational memory cells using two read multiplexes

11/24/2020

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APU

10,832,746

Non-Volatile In-Memory Computing Device

11/10/2020

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APU

10,824,394

Concurrent multi-bit adder

11/3/2020

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APU

10,817,370

Self correcting memory device

10/27/2020

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APU

10,803,141

In-Memory Stochastic Rounder

10/13/2020

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APU

10,777,262

Read data processing circuits and methods associated memory cells

9/15/2020

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APU

10,770,133

Read and Write Data Processing Circuits and Methods Associated with Computational Memory Cells that Provides Write Inhibits and Read Bit Line Pre-Charge Inhibits

9/8/2020

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APU

10,725,777

Computational memory cell and processing array device using memory cells

7/28/2020

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APU

10,635,397

System and method for long addition and long multiplication in associative memory

4/28/2020

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APU

10,534,836

Four Steps Associative Full Adder

1/14/2020

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APU

10,521,229

Computational memory cell and processing array device using memory cells

12/31/2019

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APU

10,514,914

Method for min-max computation in associative memory

12/24/2019

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APU

10,489,480

Sparse Matrix Multiplication In Associative Memory device

11/26/2019

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APU

10,402,165

Concurrent multi-bit adder

9/3/2019

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APU

10,249,362

Computational memory cell and processing array device using the memory cells for XOR and XNOR computations

4/2/2019

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APU

10,210,935

Associative row decoder

2/19/2019

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APU

10,153,042

In-Memory Computational Device With Bit Line Processors

12/11/2018

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APU

9,859,005

Memory Device

1/2/2018

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APU

9,653,166

In-Memory Computational device

5/16/2017

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APU

9,558,812

SRAM Multi-cell operations

1/31/2017

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APU

9,418,719

In Memory Computational device

8/16/2016

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APU

9,406,381

TCAM Search Unit Including a Distributor TCAM and DRAM and a Method for Dividing a Database of TCAM Rules

8/2/2016

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APU

9,197,248

Low Density parity check decoder

11/24/2015

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APU 9,076,527 Charge sharing in a TCAM array 7/7/2015 More Info
APU

8,908,465

Using storage cells to perform computation

12/9/2014

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APU

8,711,638

Using storage cells to perform computation

4/29/2014

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APU 8,341,362 System, method and apparatus for memory with embedded associative section for computations 12/25/2012 More Info
APU

8,332,580

System, method and apparatus for memory with embedded associative section for computations

12/11/2012

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APU 8,238,173 Using storage cells to perform computation 8/7/2012 More Info
APU 7,965,564 Processor arrays made of standard memory cells 6/21/2011 More Info
APU 7,268,788 Associative processing for three-dimensional graphics 11/11/2007 More Info
APU

6,757,703

Associative processor addition and subtraction

6/29/2004

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APU

6,832,234

In-place associative processor arithmetic

12/14/2004

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APU

6,467,020

Combined associate processor and memory architecture

10/15/2002

More Info

 

 

 

Memory Patents

 

Type of Patent Patent Number Title Grant Date Abstract
Memory

10,720,205

Systems and methods involving multi-bank, dual pipe memory circuity

6/21/2020

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Memory

10,659,058

Systems and methods involving lock loop circuits, distributed duty cycle correction loop circuitry

5/19/2020

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Memory

10,599,443

Systems and methods involving control-I/O buffer enable circuits and/or features of saving power in standby mode

3/24/2020

More Info
Memory

10,535,381

Systems and methods of pipelined output latching involving synchronous memory arrays

1/14/2020

More Info
Memory

10,425,070

Systems and methods involving lock-loop circuits, clock signal alignment, phase-averaging feedback clock circuitry

9/24/2019

More Info
Memory

10,303,629

Systems and Methods Involving Data Bus Inversion Memory Circuitry, Configuration(s) and/or Operation

5/28/2019

More Info
Memory

10,192,592

Systems and methods involving data bus inversion memory circuitry, configuration and/or operation including data signals grouped into 10 bits and/or other features

1/29/2019

More Info
Memory

9,966,118

Systems and Methods of Pipelined Output Latching Involving Synchronous Memory Arrays

5/8/2018

More Info
Memory

9,935,635

Systems and methods involving pseudo complementary output buffer circuitry/schemes, power noise reduction and/or other features

4/3/2018

More Info
Memory

9,859,902

Systems and methods involving fast-acquisition lock features associated with phase locked loop circuitry

1/2/2018

More Info
Memory

9,853,634

Systems and Methods of Phase Frequency Detection with Clock Edge Overriding Reset, Extending Detection Range, Improvement of Cycle Slipping and/or Other Features

12/26/2017

More Info
Memory

9,853,633

Systems and methods involving lock-loop circuits, clock signal alignment, phase-averaging feedback clock circuitry

12/26/2017

More Info
Memory

9,847,111

Systems and Methods of Pipelined Output Latching Involving Synchronous Memory Arrays

12/19/2017

More Info
Memory

9,804,856

Systems and methods involving control-I/O buffer enable circuits and/or features of saving power in standby mode

10/31/2017

More Info
Memory

9,729,159

Systems and methods of phase-locked loop involving closed-loop, continuous frequency range, auto calibration and/or other features

8/8/2017

More Info
Memory

9,722,618

Systems and methods of phase-locked loop involving closed-loop, continuous frequency range, auto calibration and/or other features

8/1/2017

More Info
Memory

9,692,429

Systems and methods involving fast-acquisition lock features associated with phase locked loop circuitry

6/27/2017

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Memory

9,679,631

Systems and methods involving multi-bank, dual- or multi-pipe SRAMs

6/13/2017

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Memory

9,613,684

Systems and methods involving propagating read and write address and data through multi-bank memory circuitry 

4/4/2017

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Memory

9,613,670

Memory systems and methods involving high speed local address circuitry

4/4/2017

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Memory

9,608,651

Systems and methods of phase-locked loop involving closed-loop, continuous frequency range, auto calibration and/or other features

3/28/2017

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Memory

9,509,296

Systems and methods of phase frequency detection involving features such as improved clock edge handling circuitry/aspects 

11/29/2016

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Memory

9,494,647

Systems and methods involving data inversion devices, circuitry, schemes and/or related aspects 

11/15/2016

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Memory

9,484,076

Systems and methods of double/quad data rate memory involving input latching, self-timing and/or other features

11/1/2016

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Memory

9,431,079

Systems and methods of memory and memory operation involving input latching, self timing and/or other features

8/30/2016

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Memory

9,413,295

Systems and Methods of Phase Frequency Detection with Clock Edge Overriding Reset, Extending Detection Range, Improvement of Cycle Slipping and/or Other Features

8/9/2016

More Info
Memory

9,412,440

Systems and Methods of Pipelined Output Latching Involving Synchronous Memory Arrays

8/9/2016

More Info
Memory

9,385,032

Systems and methods involving data bus inversion memory circuitry, configuration and/or operation

7/5/2016

More Info
Memory

9,384,822

Systems and methods involving data bus inversion memory circuitry, configuration and/or operation including data signals grouped into 10 bits and/or other features

7/5/2016

More Info
Memory

9,356,611

Systems and methods involving phase detection with adaptive locking/detection features

5/31/2016

More Info
Memory

9,318,174

Memory systems and methods involving high speed local address circuitry

4/19/2016

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Memory

9,311,971

Systems and Methods of Semiconductor Memory Devices Including Features of Output Buffer Initialization Circuit(s) and/or Multiple Power-up Detection/Handling

4/12/2016

More Info
Memory

9,240,229

Systems and methods involving control-I/O buffer enable circuits and/or features of saving power in standby mode

1/19/2016

More Info
Memory

9,196,324

Systems and methods involving multi-bank, dual- or multi-pipe SRAMs

11/24/2015

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Memory

9,159,391

Systems and methods of doubled/Quad data rate memory involving input latching, self timing and/or other features

10/13/2015

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Memory

9,135,986

Systems and methods of sectioned bit line memory arrays, including hierarchical and/or other features

9/15/2015

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Memory

9,094,025

Systems and Methods of Phase Frequency Detection Involving Features Such as Improved Clock Edge handling Circuitry/Aspects

7/28/2015

More Info
Memory

9,083,356

Systems and Methods of Phase Frequency Detection Involving Features Such as Improved Clock Edge handling Circuitry/Aspects

7/14/2015

More Info
Memory

9,053,768

Systems and Methods of Pipelined Output Latching Involving Synchronous Memory Arrays

6/9/2015

More Info
Memory

9,018,992

Systems and Methods involving phase detection with adaptive locking/detection features

4/28/2015

More Info
Memory

8,982,649

Systems and methods involving multi-bank, dual- or multi-pipe SRAMs

3/17/2015

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Memory

8,885,439

Systems and methods including clock features such as minimization of simultaneous switching outputs (SSO) effects involving echo clocks

11/11/2014

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Memory

8,817,550

Systems and Methods of Semiconductor Memory Devices Including Features of Output Buffer Initialization Circuit(s) And/Or Multiple Power-up Detection/Handling

8/26/2014

More Info
Memory

8,693,236

Systems and Methods of Sectioned Bit Line Memory Arrays

4/8/2014

More Info
Memory

8,638,144

Systems and Methods involving phase detection with adaptive locking/detection features

1/28/2014

More Info
Memory

8,593,860

Systems and Methods of Sectioned Bit Line Memory Arrays

11/26/2013

More Info
Memory

8,575,982

Systems and methods including features of power supply noise reduction and/or power-saving for high speed delay lines

11/5/2013

More Info
Memory

8,488,408

Systems and methods including clock features such as minimization of simultaneous switching outputs (SSO) effects involving echo clocks

7/16/2013

More Info
Memory

8,400,200

Systems and methods including features of power supply noise reduction and/or power-saving for high speed delay lines

3/19/2013

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Memory

8,116,161

System and method for refreshing a DRAM device

2/14/2012

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Memory

7,646,215

Efficient Method for Implementing Programmable Impedance Output Drivers and Programmable Input On-Die Termination on a Bi-Directional Data Bus

1/12/2010

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Memory

7,595,657

Dynamic Dual Control On-Die Termination

9/29/2009

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Memory

7,516,385

Test Semiconductor Device in Full Frequency with Half Frequency Tester

4/7/2009

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Memory

7,389,457

Shift Registers Free of Timing Race Boundary Scan Registers with Two-Phase Clock Control

6/17/2008

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Memory

7,355,907

Performing Read and Write Operations in the Same Cycle for an SRAM Device

4/8/2008

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Memory

7,313,040

Dynamic Sense Amplifier for SRAM

12/25/2007

More Info
Memory

7,312,629

Programmable Impedance Control Circuit Calibrated at VOH, VOL Level

12/25/2007

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Memory

7,292,490

System and method for refreshing a DRAM device

11/6/2007

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Memory

7,230,303

Semiconductor memory device with reduced soft error rate (SER) and method for fabricating same

6/12/2007

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Memory

6,806,692

Voltage down converter

10/19/2004

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Memory

6,775,193

System and method for testing multiple embedded memories

8/10/2004

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Memory

6,762,973

Data coherent logic for an SRAM device

7/13/2004

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