Technical Notes

White Papers
Memory Thermal Management 101
The New Memory Performance Figure of Merit: Address Rate
HSTL I/O Sync SRAM Board Design Guidelines
 
Application Notes
AN1024 GSI ECCRAMs™—The Benefits of On-Chip ECC
AN1023 SigmaQuad/DDR IIIe/IVe SRAM Overview
AN1022 Interfacing GSI Sync SRAMs to a Freescale MPC5554 Microcontroller
AN1021 SigmaQuad and SigmaDDR Power-Up
AN1020 Interfacing GSI Sync SRAMs to a Freescale Mutiplexed MPC567xF or PXR40xx Microcontroller
AN1019 SigmaQuad-II+ and SigmaDDR-II+ On-Die Termination (ODT)
AN1017 SigmaQuad-IIIe Input and Output Clocking Scheme
AN1016 SigmaCIO DDR-IIIe DQ ODT Control
AN1014 tKCvar Specification
AN1013 SigmaQuad Separate I/O Design Guide
AN1012 SigmaQuad Type I vs. Type II Timing Comparison
AN1010 SigmaQuad Common I/O Design Guide
AN1008 Address Pin Labeling Mismatch